Programmable chip design programs altera. We are mastering programmable logic matrices from the company – altera. Installing the driver for the USB Blaster programmer

INTRODUCTION

Usually, when someone sees a functioning board, they always ask the same questions: - Is this an Arduino? - How does it work without Arduino?

It's not a microcontroller, it's not even a processor, it's an FPGA. FPGA is a programmable logic integrated circuit, such a microcircuit consists of many identical blocks or macrocells, each manufacturer calls them differently, so for Xilinx it’s Slices (slices) for Altera - LogicElements (logical elements). These blocks are relatively simple, they can serve as several logic elements, be a small lookup table (LUT), contain a ready-made adder, multiplier, digital signal processing (DSP) unit, in general, everything that the manufacturer thinks of. The user can arrange and configure these blocks as he wishes, thus implementing quite complex digital circuits. You can implement even a microcontroller on an FPGA, for example implementing the same Arduino or a processor of your own architecture, for example, not a register processor but a stack processor, you can even implement your own FPGA on an FPGA!

Among the available budget FPGAs, two main manufacturers can be identified: Altera and Xilinx; with their products you can begin your journey of mastering these technologies. In my opinion, it is better to choose Altera chips, since their design environment is constantly updated, and if you choose one popular Xilinx XC3S500E chip, you will have to be content with the outdated ISE 14.7 environment (although it also has its advantages).

In foreign literature you can find abbreviations for FPGAs: FPGA and CPLD. CPLD (Complex Programmable Logic Device) - chips with a small number of macrocells, specialized blocks and low power consumption. A large project cannot be synthesized for this type of chip, but they are also used in practice, for example, a rare microcontroller has, say, 300 legs. Such chips are often used as interface systems, preprocessors, and I/O expanders. FPGA (Field-Programmable Gate Array) is a field-programmable gate array (FPGA), much more powerful chips compared to CPLD, but consumes more power and costs significantly more. To reduce the cost of die area, FPGA chips can contain ready-made functions, such as digital signal processing units (DSP units), embedded processors, and embedded memory. FPGAs are widely used for testing and verifying designs, in so-called pre-silicon validation, thereby reducing costs and time before product release. FPGA chips can be reconfigured at almost any time; developments are currently underway, for example at Intel, to combine the architectures of a conventional processor and an FPGA chip. Xilinx already has such solutions - Zynq, but we will not talk about them for now.

We will talk about simpler things, especially since I got my hands on a development kit: Cyclone IV 4 FPGA Core Board and Altera USB Blaster Downloader PLD Development kit for $35, purchased on AliExpress.

1 Demo board Cyclone IV 4 FPGA Core Board, brief description

Rice. 1 - Demo payment Cyclone IV 4 FPGA Core Board

The board (Fig. 1) has an EP4CE6E22C8N chip installed, its characteristics:

The board has:

1. Flash Memory – When power is applied, the FPGA will be configured to be implemented in flash memory. You can synthesize your project and write into this flash
2. 25 MHz quartz is a reference clock frequency generator, it is at this frequency that all our projects will operate, our FPGA can support up to 10 such channels.
3. LEDs – 10, buttons – 2.
4. I/O pins 61 + 2 ground, 1 not connected. You can connect a variety of devices. DAC-ADC, accelerometers and gyroscopes, character and graphic displays, like Arduino.
5. Power supply via USB, or external 5V.

The kit also includes a JTAG programmer, Altera USB Blaster.

2. Quartus II environment and our first project

To work with this FPGA we need to download the official development environment - Quartus II Web Edition, it's free. We go to the official website http://dl.altera.com/15.0/?edition=web, at the time of writing version 15.0 is the newest, if it is newer, download it.

Choose:

Rice. 2 - select the necessary Altera products

And click the download button (Download Selected Files). After which we will be asked to register, register, download and install.

Let's create our first project.

Launch Quartus, select the main menu File -> New Project Wizard, the introduction window appears, click next. Next you need to specify the directory for the project and its name, the third field is the name of the top module, you will see later what it is. We select the folder where we want to save the project and come up with a name, I have test1.

Rice. 3 - new project wizard window

Click next, we are asked whether it is an empty project or a Project template. Leave empty, next. Next we are asked to add existing files, we have nothing, since we are just starting our journey, click next.

Next, we need to select our chip; this can be done at any time. Select as in the picture, Family – Cyclone IV E, specific device selected in “Available devices” and select our EP4CE6E22C8N chip, it’s at the very beginning. If you have another, find yours, it is important. Click next.

Rice. 4 -

A window will appear - selecting design tools, debugging, skip this for now, click next and then finish.

Rice. 5 - Window "Assinments-Deice"

In the window, select the “Unused pins” item. This setting determines what happens to unconnected pins. This may be important; in your project you are unlikely to use all the pins, and the unconnected ones may in fact be connected to ground or power (well, you never know who wired the board). If you apply a one to a grounded pin, it will burn out, so you need to carefully monitor this.

By default, the unused pins “As input tri-stated with weak pull-up” (input pins are in the third state with high impedance, with a weak power pull-up), you can leave or select “As input tri-stated”. You can read about the pull-up resistor on Wikipedia https://ru.wikipedia.org/wiki/Pull-up_resistor. In digital technology there can be three states, a logical one is the supply voltage or a high level, a logical zero is when the pin is connected to ground or a low level and high impedance state. High impedance condition- this is when a pin has a very high resistance and practically does not affect the wire to which it is connected; this state is necessary, for example, when organizing buses, when many devices are connected to one wire and inactive devices do not interfere with operation.

Rice. 6 - “Device and Pin Options” window, Unused Pins

We connect it all in the “Assignment Editor”

Rice. 7 - Call “Assignment Editor” from menu or panel

In the window that appears, do it as I did, or, if absolutely correct, then according to the diagram of your board.

Rice. 8 - Assinement Editor

In the “To” column, enter the name of the input or output. In the “Assignment Name” column, select “Location”. In the “Value” column there is the pin number of the microcircuit, according to the board diagram (I have pin numbers written directly on the board).

You also need to specify what to do with the buttons, which are connected with one leg to the ground and the other to the input of the chip. When you press on the leg there will be a low level, but without pressing, it’s unclear, the chip’s leg will just hang in the air, which is very bad. You need to connect the chip input to power either with a resistor on the board or in a more elegant way in the “Assignments Editor”. In the “Assignment Name” column, select “Weak Pull Up resistor” for the key* group (the group is indicated by an asterisk).

Rice. 9 - Assignment Editor

Next, you need to create a description of the top-level module, which will work directly with the chip legs; all other modules will work only with it. In the main menu, click New, and select "Design Files-> Block Diagram/Schematic File".

Rice. 10 - New files dialog

In the window that opens, select the “Pin Tool” and place the input and output (input and output pins) on the diagram. We rename the input as key, the output as led and connect them with a conductor. Save and click "Start Compilation".

Rice. 11 - Graphic description window, Pin Tool and Start Compilation highlighted

After compilation, we had warnings, we ignore them for now, they relate to unconnected pins, the absence of a clock signal and the description for the “Timing Analyzer”.

We connect the demo board and programmer, select the “Programmer” tool. The window should say “USB-Blaster”, if not, then click “Hardware Setup” and try to figure out why not, most likely the drivers are not installed, look in Windows devices, we are looking for unidentified devices, maybe there is a problem with the cable. If everything is fine, click “Auto Detect” and select our chip.

Rice. 12 - Programmer Window

Double-click in the “File” field and select the file to write to the FPGA (located in the output_files folder of our project), check the “Program / Configure” field, and click the “Start” button.

Rice. 13 - Programmer window, our chip is already configured

Congratulations on your first FPGA configuration! Diode D1 should light up, when you press key1 it should go out (since the button closes the leg to ground), then we will do something about it)

ALTERA programmable logic integrated circuits and MAX+PLUS II computer-aided design system

Programmable logic integrated circuits (FPGAs), or in foreign literature referred to as PLDs (programmable logic devices), are semi-custom digital LSIs, which, thanks to their architectural and technological features, can be developed and manufactured without specialized technical equipment. FPGAs appeared on the world market in the mid-80s. And they immediately became widespread, moving the process of creating a specialized LSI from the factory to workplace designer. The LSI development cycle has been reduced to several hours, and the associated costs have been significantly reduced.

Since the beginning of the 90s. The greatest demand is for FPGAs that have:

high logic integration based on CMOS technologies;

speed up to 80 -100 MHz and higher;

Possibility of programming (loading internal configuration) without a programmer.

All these requirements are met by FPGAs from ALTERA (USA), a world leader in the field of FPGAs. Currently, ALTERA produces seven families of FPGAs of various architectures [14].

In Russia, the most famous FPGAs are the Classic family, produced for some time by INTEL. The main advantages of these microcircuits are simplicity, low cost, easy-to-install DIP packages, micro-energy consumption in static mode and the ability to be supported by domestic means (CAD FORS+, Blitz, Sterkh, Forsys programmers). FPGA EP220 replaces any 1556 series microcircuit (HP4, HP6, HP8, XL8).

All FPGAs are manufactured using ultraviolet eraseable CMOS (EPROM) technology, which provides the following power consumption parameters:

in static mode - 10-30 µA;

at a frequency of 1 MHz - 2-8 mA;

with increasing clock frequency - 1 mA/MHz.

To reduce the price by 30-40% during mass production of products, all FPGAs are also produced in plastic packages (DIP and PLCC) with one-time programming.

The disadvantages of FPGAs of the classic family are the relatively low degree of integration and some architectural features: the lack of input for triggers to be set to “1” (SET), blocking of contacts when implementing internal memory elements.

FPGAs of the MAX7000 and FLASHlogic families, which have a matrix architecture, i.e. contain programmable matrices of logic gates “AND”, “OR” and flip-flops.

The MAX7000 family consists of seven chips with integration levels ranging from 1,200 to 10,000 equivalent logic gates, containing from 32 (EPM7032) to 256 (EPM 7256) flip-flops.

Additionally, FPGA EPM7032V is produced - a functional analogue of the EPM7032 microcircuit with a supply voltage of 3.3 V.

The MAX7000 family of FPGAs are manufactured using electrically erasable CMOS (EEPROM) technology. They provide:

minimum signal propagation delay from input to output 5 ns;

maximum clock frequency 190 MHz;

up to 100 programming/erase cycles.

The MAX7000 family of FPGAs have a flexible architecture. Their macrocells contain two independent feedback lines; from the trigger and from the contact. This allows the flip-flop to be used as an internal register and the pin to be used as an input port at the same time. Additional FPGA resources are expansion terms - conjunctors whose inverse outputs form feedbacks with a matrix of elements “AND”. Terms allow you to generate control signals (for example, CLK, SET, RESET) without spending macrocells. As a result of the redistribution of terms between macrocells, the number of inputs of the “OR” elements can be increased to 32.

Each macrocell has an individual turbo bit, the programming of which allows you to reduce power consumption with a slight decrease in performance. Beginning in 1996, all MAX7000 family FPGAs will be available in the ISP (in system programmable) variant. This will allow you to program and erase the circuit directly on the working board through the 4th signal interface connected to the computer port. The presence of a programmer becomes optional, which greatly simplifies and reduces the cost of using FPGAs.

The MAX7000 family FPGAs have low cost. For example, the price of the EPM7032 chip is less than 7, and the EPM7128 chip is less than 25.

With the advent of the MAX7000 family, the practical value of the previously produced FPGAs of the MAX5000 family has significantly decreased, because analogues of all microcircuits appeared (for example, EPM5128 - EPM7128) with best characteristics performance and energy consumption at lower prices.

MAX+PLUS II is an automated programmable logic integrated circuit (FPGA) design system developed by Altera Corporation, a global leader in FPGA manufacturing.

MAX+PLUS II is a multifunctional software product that provides the designer with the ability to completely design an FPGA, from entering the circuit that the designer intends to implement on the FPGA and ending with programming the FPGA itself on the programmer.

MAX+PLUS II offers the following user options:

input of the internal structure of the FPGA by graphical input of the functional diagram;

entering the internal structure of the FPGA using a programming language high level Altera Hardware Description Language (AHDL), which is fully built into the MAX+PLUS II shell;

modeling of FPGA operation in the form of timing diagrams;

If you have a programmer, write the designed structure to the FPGA, etc.

When describing the internal structure of an FPGA using AHDL, several options are possible.

In the first option, describe the structure in primitives, i.e. using simple functions such as RS-trigger, D-trigger, T-trigger, JK-trigger, etc.

In the second option, carry out the description using primitives and mega-functions.

Mega functions are complex logical functions such as counter, multiplexer, decoder, register, etc.

The advantage of the first option is that the translator spends less time converting the simplest AHDL functions into machine codes.

The disadvantages of this option are the large volume of program text and the need detailed description the entire system.

In the second option, when using mega-functions, there is no need for a detailed description of the elements in the sense that the programmer sets only the parameters of a complex logical function. For example, using the lpm_counter mega-function, a counter can be described by specifying only the clocked input and the width of the counter itself. This significantly reduces the volume occupied by the program text, and also allows you to slightly reduce the time it takes to write a program.

The disadvantage is that it takes more time to translate the program into machine codes compared to the first option.

But in the end the result is the same, so the writing style software product depends entirely on the designer.

When debugging a written software product, SIMULATOR MAX+PLUS II allows you to examine in detail the result of the FPGA operation in the form of timing diagrams. The designer can select various outputs and intermediate states described in the program, as well as specify various input actions.

Were you waiting for a sign? Here he is!

For many years I was hesitant to start programming FPGAs because it was difficult, expensive and painful (as it seemed to me). But it’s good to have friends who help you take the first step. And now I don't understand one thing - WHY DID I WAIT SO LONG?

Now I will help you take the first step too!

Why do I need it?

Do you want to finally breathe freely? Go ahead!

The joy of developing on FPGAs

That evening I realized: HERE IT IS! This is the platform where I can quickly and easily turn my thoughts into actually working hardware!

Why is that?

• Universality of knowledge- when changing the MK model, you need to read the documentation. When changing the manufacturer of the MK, you need to read the documentation. You need to constantly read the docs, constantly keep a lot of information in your head. When developing on an FPGA, if you know Verilog or VHDL, then you can not only program any FPGA from the line of one manufacturer, but also, if you wish, switch to another (Altera, Xilinx). Although there will be moments when mastering a different development environment and subtle hardware issues, the very essence of the approach to designing devices in HDL will not change from this.
• From idea to hardware- when developing a project, if you lack one microcontroller, you have to choose another. In principle, you can make assumptions about whether this MK will cope or not cope with the project. Or there is a specific MK and you are trying to fit a project into it. Most often this is the case. It reminds me a little of my grandfather’s approach, who makes a ladder out of what he has in the shed. Although you can design a staircase, buy boards that will fit... From idea to hardware, and not vice versa.
• Ease of use of other people's developments- you can take someone else's module and apply it in your project. You can understand from the code how it works. Even if it is for xilinx, and you are doing it under altera. Sometimes this doesn't work out well, but it's easier than, for example, adding binary libraries to a C++/Qt project
• Block independence. Blocks in HDL are like pure functions in language. Depends only on input signals. The developed and debugged module will continue to work correctly, no matter how the project grows. Nothing from the outside will affect the correct operation of it from the inside. And in general, you can forget how it works - it's a black box. Plus, the blocks work parallel.

Problem of choice

Manufacturer

Language

Development board

In the Altera family, for reasonable money we can buy boards with CPLD MAX II with 240, 570 and 1270 elements, or older FPGA chips such as Cyclone 1, 2, 3, 4 with up to 10,000 or more cells. How to choose?

Even on the basis of 240 cells, the Mars Rover project does just a huge number of projects. I strongly recommend that you read it to get a rough idea of ​​the complexity of projects that can fit into 240 cells. On the other hand, there are projects that are completely programmed for a hardware copy of a specific PC, including the processor and all the logic around it (NES, Speccy, Orion, YuT-88, etc). This already requires five, ten or more thousand cells. Plus, these boards contain additional external devices.

Therefore, I would advise taking something between 240 and 10,000 cells, with a preference for larger ones depending on the available funds. On a debug board, extra cells are not a big deal, but if there aren’t enough of them, there’s nothing you can do about it. Then, when the device is debugged, it will become clear how many cells are needed, buy at required quantity, without unnecessary “body kit”, cheaper and left in the finished device.

What really differentiates MAX from Cyclones, besides the number of cells, is:
1) The MAX series does not have a PLL inside. Each development board has an oscillator, usually 50 MHz. This will be enough for the majority of projects. All synchronization will occur by dividing 50 MHz by some value. Or, you can take an external generator and feed it to a separate FPGA input. What if you need a frequency higher than 50 MHz? I was unable to immediately find oscillators above 50 MHz. But this is where PLL, which is built into Cyclones, comes to the rescue. On it you can multiply the frequency, for example, up to 100 MHz.
2) The Cyclone series has built-in hardware multiplication units. Their number depends on specific model- here you can just “look at the instructions” to find out how much. If you plan to do some kind of DSP, then they will come in handy: they will save cells and increase speed. On the other hand, if there are no multipliers, they can be synthesized, but a small FPGA may not have enough resources for this.

In all other respects, I have a “fit/not fit” criterion. Debugging on a board that is obviously larger than needed, followed by filling it with the minimum required for this.

How much money is needed?

Programmer
I believe that I do not have time to solder programmers in bulk.

300 rubles. I got mine on eBay, it looks like this:

Development board
The choice is wide, depending on the amount of money.

First level 350 - 550 rubles. These are boards based on MAX II (or cells). May be suitable for initial familiarization and further integration into end devices. The board has a generator, a couple of buttons, a couple of LEDs, and the remaining 80 pins at your discretion.

power unit
It's a must have, but it's not always included. You will need a 5 volt power supply and a current of 2A.

Average level from 900 to 1500 rubles. These are Cyclone 1, 2, 3, 4 boards, differing mainly in the number of cells.
They are marked something like this:
E.P. 2 C 5 T144 - Cyclone 2 approximately 5k cells
E.P. 4 C.E. 6 E22C8N - Cyclone 4 approximately 6k cells
E.P. 2 C 8 Q208C8N - Cyclone 2 approximately 8k cells

You may notice that Cyclone 3 may have more cells than Cyclone 4.

Here are some options:

835 rubles.
ALTERA FPGA CycloneII EP2C5T144 Minimum System Board for Learn good

880 rubles
Altera CycloneII EP2C5T144 FPGA Mini Development Learn Core Board E081

1265 rubles
EP2C8 EP2C8Q208C8N ALTERA Cyclone II FPGA Evaluation Development Core Board

Advanced boards . These are the boards on which additional modules(UTP, USB, AUDIO), connectors (SD, VGA), buttons, switches, LEDs, seven segment indicators etc. Or there may be a base board, and expansion boards may be attached to it separately.

I have the following set working - board + expansion board:
Altrea EP4CE10E22 FPGA CORE Board+ Device Board USB/Sound/Ethernet/SD Card/VGA
2760 rubles

Here is the main board. It has 2 LEDs, 2 buttons, 4 switches, a seven-segment indicator and a RAM chip.

Expansion board. It contains SD, VGA, as well as USB controllers (High Speed ​​USB2.0 Chip: CY7C68013A), AUDIO (Sound Card up to 96kHz/32bit ADC/DAC: WM8731S), UTP (100M Ethernet interface: DM9000A):

These boards are simply inserted into one another, but I still have it in a drawer. For my crafts, I have a breadboard, which I connect to with a cable that comes with the kit. A 5 volt power supply is also included.

The first company to enter the market with programmable integrated circuits (FPGAs). Altera offers two CAD systems: MAX+PLUS II and Quartus II. Each CAD system supports all design phases: Design Input, Compilation, Verification and Programming. Each CAD system has a Tutorial, which is installed when installing the package. The Tutorial consists of classes that walk you through the entire design cycle from design input to chip programming. During installation, files are also installed that describe the project so that while studying Tutorial you can skip individual lessons and use ready-made files. For example, you can skip "Project Input" and go to "Compile" the project using ready-made files.

The MAX+PLUSII system has efficient synthesis algorithms that allow maximum use of chip resources and big set tools for device verification at the functional and temporal design level.

The company also distributes specialized Design Kits that facilitate the use of FPGAs in specific tasks. Such kits contain CAD-compatible logic functions and a methodology for using them. Of interest are the Design Kit, dedicated to the development of products in the PCI bus standard and digital signal processing circuits. The first includes template functions for implementing controllers (Master/Slave) and parity checking circuits. The second is focused on the efficient implementation of circuits such as multipliers, FIR filters, floating point operations, Fourier transform

MAX is designed to interface with VHDL, EDIF, Verilog standards. Any CAD configuration imports input data in EDIF format and produces design results in all listed formats. Using translator programs, it is possible to import information into the text description format of CAD MAX from files in the PDS (CAD PLDShell, PALASM) and XNF (CAD XACT from Xilinx) formats. It is possible to convert diagrams created in the OrCAD system into files in the format of your own graphic editor.

Altera offers free CAD versions MAX+PLUS II BASELINE and Quartus II Web Edition, which support all stages of design from design input to programming. Limitations are the number of chips supported and some features for Quartus II. Free versions CAD can be downloaded from the Altera website (https://www.altera.com/support/software/download/sof-download_center.html).

1 Pin assignment in the Quartus II project

On the menu Assignments Device… select the FPGA into which you are going to “upload” the project. In Group Device Family you need to select the family to which your FPGA belongs. In field Available devices select your FPGA model. For example, I have Cyclone II, model EP2C5T144C8.

In Group Show in "Available devices" list You can sort devices by case type ( Package) or by the number of pins ( Pin count) to quickly find your FPGA model.

It would be useful to specify the state of the unconnected FPGA legs. Click the button Device and Pin Options…, go to point Unused Pins, and indicate the state of the pins.

After specifying the FPGA model, close the window Device by pressing the button OK.

If you want the synthesizer to assign functions to the pins itself, then you don't have to do anything else. And in order to manually assign FPGA pins, go to the menu Assignments Pin Planner or press the key combination Ctrl+Shift+N.

The pin assignment tool will launch. Pin Planner. Below is a list of I/O pins used in your project with their corresponding names. Node Name.

Now in the column Location you need to specify pin numbers. Double-click on the corresponding cell and select the output number, or enter the number from the keyboard. The pin numbers will depend on your breadboard. For example, in my board, the CLK clock pulse, according to the manual, is on pin 17, and I will assign free pins 94, 97, 100, 103 and 93 to the OUT1...OUT5 outputs.

Once all pins have been defined, the Pin Planner window Pin Planner can be closed. Now compile the project: Processing Start Compilation or Ctrl+L .

2 Driver installation for USB Blaster programmer

Let's connect the USB Blaster programmer to the computer (if you don't have one, you can buy it on Ali Express). The first time you connect, you need to install the driver. It is installed in the standard way, and is located in the Quartus directory, in the folder drivers: C:\altera\13.0sp1\quartus\drivers

After installing the driver, the programmer will appear in the device manager as Altera USB-Blaster.

Altera FPGAs support several programming modes. First, let's look at loading the firmware into the FPGA via JTAG interface. Connect the programmer to the JTAG connector on the FPGA board.

Let's launch the programming tool: Tools Programmer.

Let's add a programmer. To do this, press the button Hardware Setup… and select the connected USB Blaster from the drop-down list. Let's close the window Hardware Setup.

In the programmer window Programmer click the button Auto Detect to have Quartus try to automatically detect the connected FPGA and the *.sof firmware file.

The firmware file is created by Quartus by default during compilation and saved in the directory output_files, unless otherwise specified.

In the window Programmer select mode JTAG, check the box Program/Configure and press the button Start. The firmware will be written to the FPGA memory.

In order for the firmware to be saved in ROM, we write the firmware in Active Serial mode.

Connect the programmer cable to the connector AS or Active Serial. Run the firmware program: Tools Programmer.

Select mode Mode Active Serial. Agree when answering a clarifying question.

Add the firmware file by clicking the button Add File... In the project subdirectory output_files find the file with the extension .pof.

After opening the firmware file, check the boxes Program/Configure and, if desired, the rest.

Note the configuration memory type in the column Device: It must match the type of memory you have installed on your board.

Click the button Start to load the firmware into the FPGA configuration memory.

To convert and configure firmware files, there is a tool that is accessible from the menu File Convert Programming Files….